View CY24204_4146166.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY24204
MediaClockTM DTV, STB Clock Generator
Features
* Integrated phase-locked loop (PLL) * Low jitter, high-accuracy outputs * VCXO with Analog Adjust * 3.3V operation Part Number CY24204-3 CY24204-4 Outputs 4 4 Input Frequency 27-MHz Crystal Input 27-MHz Crystal Input
Benefits
* Internal PLL with up to 400-MHz internal operation * Meets critical timing requirements in complex system designs * Large 150-ppm range, better linearity * Enables application compatibility Output Frequency Range Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable) Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased VCXO pull range) Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased output drive strength)
CY24204-5
4
27-MHz Crystal Input
Block Diagram
XIN XOUT VCXO P Q VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 CLK2 REFCLK1 REFCLK2 (-3,-4,-5)
Pin Configurations
16-pin TSSOP
OSC.
XIN VDD AVDD VCXO AVSS VSSL REFCLK2 REFCLK1
1 2 3 4 5 6 7 8
16 15
XOUT OE FS1 VSS CLK1 VDDL FS0 CLK2
PLL
24204-,3,4,5
14 13 12 11 10 9
FS0 FS1 OE
VDDL
VDD
AVDD
AVSS
VSS
VSSL
Cypress Semiconductor Corporation Document #: 38-07450 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 19, 2005
CY24204
Frequency Select Options
OE 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CLK1/CLK2[1] off off off off 27 27.027 74.250 74.17582418 REFCLK 1/2 27 27 27 27 27 27 27 27 Unit MHz MHz MHz MHz MHz MHz MHz MHz
Pin Description
Name XIN VDD AVDD VCXO AVSS VSSL REFCLK2 REFCLK1 CLK1 FS0 VDDL CLK2 VSS FS1 OE XOUT
Note: 1. "off" = output is driven HIGH.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Reference Crystal Input. Voltage Supply. Analog Voltage Supply. Input Analog Control for VCXO. Analog Ground. CLK Ground. Reference Clock Output. Reference Clock Output.
Description
27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). Frequency Select 0, Weak Internal Pull-up. CLK Voltage Supply. 27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). Ground. Frequency Select 1, Weak Internal Pull-up. Output Enable, Weak Internal Pull-up. Reference Crystal Output.
Document #: 38-07450 Rev. *C
Page 2 of 6
CY24204
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage (VDD, AVDDL, VDDL)..................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-Condensing).... -55C to +125C Junction Temperature ................................. -40C to +125C Data Retention @ Tj=125C..................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V
Pullable Crystal Specifications
Parameter FNOM CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Ratio of third overtone mode ESR to fundamental mode ESR Crystal drive level Fundamental mode Ratio used because typical R1 values are much less than the maximum spec No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. - - - 3 - 300 - - 180 14.4 - 0.5 - - - - 18 Typ. 27.0 14 Max. - - 25 - 2 - -150 7 250 21.6 fF mW ppm ppm pF Unit MHz pF
Third overtone separation from 3*FNOM High side Third overtone separation from 3*FNOM Low side Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance
Recommended Operating Conditions
Parameter VDD/AVDDL/VDDL TA CLOAD tPU Operating Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.135 0 - 0.05 Typ. 3.3 - - - Max. 3.465 70 15 500 Unit V C pF ms
DC Electrical Specifications
Parameter[2] IOH1 IOL1 IOH2 IOL2 VIH VIL IVDD IVDDL CIN fXO fXO VVCXO RUP Name Output High Current for -3,-4, Output Low Current for -3,-4 Description VOH = VDD - 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V Min. 12 12 18 18 0.7 - - - - Nominal pullability for -1,-2,-3,-5,-6 Extended pullability for -4 150 - 0 - Typ. 24 24 26 26 - - - - - - 200 - 100 Max. - - - - - 0.3 25 20 7 - - VDD 150 Unit mA mA mA mA VDD VDD mA mA pF ppm ppm V k
Output High Current for -5 VOH = VDD - 0.5, VDD/VDDL = 3.3V Output Low Current for -5 VOL = 0.5, VDD/VDDL = 3.3V Input High Voltage Input Low Voltage Supply Current Supply Current Input Capacitance VCXO pullability range VCXO pullability range VCXO input range Pull-up resistor on inputs VDD = 3.14 to 3.47V, measured at VIN = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 3.47V)
Note: 2. Not 100% tested.
Document #: 38-07450 Rev. *C
Page 3 of 6
CY24204
AC Electrical Specifications
Parameter[2] DC ER1 EF1 ER2 EF2 t9 t10 Name Output Duty Cycle Description Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD Min. 45 0.8 0.8 1.0 1.0 - - Typ. 50 1.4 1.4 1.8 1.8 120 - Max. 55 - - - - - 3 Unit % V/ns V/ns V/ns V/ns ps ms
Rising Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Falling Edge Rate for -3,-4 Rising Edge Rate for -5 Falling Edge Rate for -5 Clock Jitter PLL Lock Time Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. CLK1, CLK2 Peak-Peak period jitter
Test and Measurement Set-up
VDDs 0.1 F DUT
Outputs CLOAD
GND
Voltage and Timing Definitions
t1 t2 VDD 50% of VDD Clock Output 0V
Figure 1. Duty Cycle Definition
t3 t4 V
DD
80% of V DD Clock Output 20% of V DD 0V
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Document #: 38-07450 Rev. *C
Page 4 of 6
CY24204
Ordering Information
Ordering Code Standard CY24204ZC-3 CY24204ZC-3T CY24204ZC-4 CY24204ZC-4T CY24204ZC-5 CY24204ZC-5T Lead-free CY24204ZXC-3 CY24204ZXC-3T CY24204ZXC-4 CY24204ZXC-4T CY24204ZXC-5 CY24204ZXC-5T Z16 Z16 Z16 Z16 Z16 Z16 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP Commercial Commercial Commercial Commercial Commercial Commercial 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Z16 Z16 Z16 Z16 Z16 Z16 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP Commercial Commercial Commercial Commercial Commercial Commercial 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Package Name Package Type Operating Range Operating Voltage
Package Drawing and Dimensions
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05gms
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
51-85091-*A
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07450 Rev. *C
Page 5 of 6
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY24204
Document History Page
Document Title: CY24204 MediaClockTM DTV, STB Clock Generator Document Number: 38-07450 REV. ** *A *B *C ECN NO. 123842 128775 214080 310573 Issue Date 04/10/03 09/0803 See ECN See ECN Orig. of Change CKN IJA RGL RGL New Data Sheet Added -4 and -5 parts Added -6 part Removed -1,-2 and -6 parts Added Lead-free devices for -3, -4, and -5 parts Description of Change
Document #: 38-07450 Rev. *C
Page 6 of 6

▲Up To Search▲

Price & Availability of CY24204

	To Download CY24204 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .